"Explore Beyond Academics.. "


The object of the research group is find effective solutions for Low power Testing, test Data Volume reduction, LBIST, MBIST and Hardware Authentication., And to convert the solutions to publications and patents


Faculty / Mentor : Mrs.Nayana M

Current Students : Anish A | Bibi | Sindhu | Bhavana | Hajira


Students Alumni :

  • Praveen T S
    -   Imspired Solutions,

  • Ranjith
    -   Imspired solutions

  • Praveen S
    -   RV college of engineering

  • Arpitha
    -   Dayanand sagar college of Engg

  • Prasad
    -   UTL Technologies Limited

  • Ravi Kiran
    -   Intel India Pvt Ltd.

  • Gowthami
    -   Intel India Pvt Ltd.

  • Rithesh
    -   Imspired solutions

  • Karthik A
    -   Dxcorr Hardware

  • Priya D S
    -   PESIT

  • Bhargav
    -    Ultran Technologies


The Lab is facilitated with Research Suite from Cadence where the following tools are used:

  • Cadence RTL compiler
  • Cadence Encounter Test
  • Cadence NCSIM
  • Cadence SoC encounter
  • Cadence Encounter timing system

Advanced tools Codes
Synthesis
Encounter RTL Compiler CPU Accelerator Option RC302
Encounter RTL Compiler Low Power Option RC310
Encounter RTL Compiler Advanced Physical Option RC340
C-to-Silicon Compiler - L CTS102
Encounter RTL Compiler CPU Accelerator Option RC302
Encounter RTL Compiler Low Power Option RC310
Test
Encounter™ True Time ATPG Advanced ET023
Encounter Diagnostics Basic ET010
Option to RC - DFT Architect Advanced ET021
Encounter Test LBIST Option ET025
Encounter Test Advanced MBIST Option ET024
Encounter™ True Time ATPG Advanced ET023
Signoff Power Analysis
Voltus IC Power Integrity Solution Advanced Analysis GXL VTS201
Signoff Timing Analysis
Tempus Timing Signoff Solution XL TPS200
Tempus Timing Signoff Solution TSO TPS300
Tempus Timing Signoff Solution MP TPS400
Digital Implementation
Encounter™ Low Power GXL Option EDS10
Encounter™ Advanced Node GXL option EDS30
Encounter Mixed Signal GXL Option EDS20
Encounter Giga Scale GXL Option EDS70
Encounter DFM GXL Option EDS50

  1. Design and Verification of PMBIST

  2. Low hardware cost LBIST

  3. Detection and Analysis of Hardware
    Trojan using scan power analysis

  4. Hardware trojan self detection

  5. Implementation of Multi-VDD technique
    for complex SoC


This research group closely works with Imspired solutions who provides services in ASIC design, Verification, and DFT. Students in this reserach group are given with industrial projects from Imspired solutions Ltd.


  1. Gowthami M R, Bhargav Ram B V, G. Harish, Dr. Siva Yellampalli, “Modified Low Power Scan Based Technique”, 19th International Symposium on VLSI Design and Test 26-29 2015.
  2. Rithesh M, Bhargav Ram B V, G. Harish, Dr. Siva Yellampalli, “Detection and Analysis of Hardware Trojan using Scan Chain Method”, 19th International Symposium on VLSI Design and Test 26-29 2015.
  3. Ravi Kiran N, Karthik A, G. Harish, Dr. Siva Yellampalli, “Low Power and Hardware Cost STUMPS BIST”, 19th International Symposium on VLSI Design and Test 26-29 2015.
  4. Gowthami M R, Ravi Kiran N, Harish G and Dr. Siva Yellampalli, “Test Power Aware STUMP BIST”, International Conference on Smart Technologies and Management for Computing, Communication, Control, Energy and Materials, 6-8 May 2015.
  5. B. V. Bhargav Ram N, Harish G and Dr. Siva Yellampalli, “Stepped Segment LFSR for Low Test Power BIST”, International Conference on Smart Technologies and Management for Computing, Communication, Control, Energy and Materials, 6-8 May 2015.
  6. N. Ravi Kiran, Rithesh M, Harish G and Dr. Siva Yellampalli, “Hardware Trojan Self-Detector”, International Conference on Smart Technologies and Management for Computing, Communication, Control, Energy and Materials, 6-8 May 2015.
  7. M. Rithesh, Harish G and Dr. Siva Yellampalli, “Detection and Analysis of Hardware Trojan using Dummy Scan Flip-Flop”, International Conference on Smart Technologies and Management for Computing, Communication, Control, Energy and Materials, 6-8 May 2015.
  8. Mohammed Musab, Dr. Siva Yellampalli, “Study and Implementation of Multi-VDD Power Reduction Technique”, International Conference on Computer Communication and Informatics 08-10 2015.
  9. Karthik A, Dr. Siva Yellampalli, “Compartive Analysis of Various off – Chip Bus Encoding Technique”, International Conference on Computer Communication and Informatics 08-10 2015.
  10. Ravi Kiran N, Dr. Siva Yellampalli, “Low Hardware Cost Stumps BIST”, International conference on Circuits, Communication, Control and Computing I4C2014, November 21-22, 2014.
  11. Shashidhara HB, Dr. Siva S Yellampalli, “Board Level JTAG/Boundary Scan Test Solution”, International Conference on Circuits, Communication, Control and Computing- 14C2014, November 22-22, 2014.
  12. S Praveen, Siva Yellampalli, G Harish, “Optimization of Test Time and Fault Grading of Functional Test Vectors using Fault Simulation Flow”, 2014 ICECCE International Conference on 17-18th November 2014.
  13. Nayana M, Siva Yellampalli, G Harish, “Modified Low Power STUMPS Architecture”, 2014 ICECCE International Conference on 17-18th November 2014.
  14. Praveen Sakrappanavar, Siva Yellampalli, G Harish, “Comparative Analysis of Scan Compression Techniques”, 2014 ICECCE International Conference on 17-18th November 2014.
  15. Nayana M, G. Harish, Siva Yellampalli, “Comparative Analysis of BIST Architectures”, International Conference on Advanced trends in VLSI & Signal Processing, on 13-14th August 2014.
  16. Shilpa Patil , G. Harish, Siva Yellampalli, “Comparative Analysis of Different LFSR Architectures ”, International Conference on Advanced trends in VLSI & Signal Processing, on 13-14th August 2014.
  17. Praveen Sakrappanavar, G. Harish, Siva Yellampalli, “Scan Compression and Area Optimization for Homogeneous Multi-Core Designs”, International Conference on Advanced trends in VLSI & Signal Processing, on 13-14th August 2014.
  18. Arpitha H N, G. Harish, Siva Yellampalli, “Analysis of Test Overhead in Boundary Scan Architecture”, International Conference on Advanced trends in VLSI & Signal Processing, August13-14, 2014.
  19. S. Praveen, G. Harish, Siva Yellampalli, “Effective ATPG Flow for Optimization of Test Time and Fault Coverage”, International Conference on Advanced trends in VLSI & Signal Processing, August13-14, 2014.

From the management of UTL technologies 3000 Rs grant is given for each and every paper which is selected for IEEE conference/Journal.


Faculty

Mrs. Nayana M

Email : nayana.m@utltraining.com


This research group primarily aims on VLSI design verification of complex Ips and interconnects. Higher abstraction level languages and hardware verification languages are used for verifying complex SOCs. The aim is to create VIPs( verification intellectual property) for complex SOCs.


Faculty : Mr. Pradeep S V


Current Students : Kruthika | Divya | Sanjeev Reddy


Students Alumni : Shalini (Live wire) | Vishwanth Matapathi.


The Lab is facilitated with Research Suite from Cadence where the following tools are used.

  • Cadence RTL compiler
  • Cadence Encounter Test
  • Cadence NCSIM
  • Cadence SoC encounter
  • Cadence Encounter timing system

  1. Bus protocol verification as UART, SPI, GPIO, AXI.

  2. Test Structures for NoC fabric

  3. ARM NIC Protocal Verification

  4. Test and Verification of Compiler

  5. Design and verification of memory control for Flash Memory


This research group closely works with Imspired solutions who provides services in ASIC design, Verification, and DFT. Students in this reserach group are given with industrial projects from Imspired solutions Ltd.


  1. Salman Khan B R, Arun Patro, Siva S Yellampalli, “Design of UART Protocol with Interrupt Logic and Status Register”, International Journal of Innovative Technology and Exploring Engineering (IJITEE), ISSN: 2278- 3075, Vol. 4, Issue. 7 December 2014.

  2. Sunith Kumar V, Arun Patro, Dr. Siva Yellampalli, “Design of the PCI Master with LDPC Technique”, International Journal of Emerging Technology and Advanced Engineering, Vol. 5, Issue. 1, January 2015.

  3. Sawthi S, Arun Patro, “Design of a Novel Counter Based NCO”, International Journal of Innovative Research in Computer and Communication Engineering (IJIRCCE) Vol. 3, Issue. 10, October 2015.

  4. Nanda Hanamant Khanapur, Arun Patro, “Design and Implementation of Enhanced version of MRC6 algorithm for data security”, International Journal of Advanced Computer Research Vol. 5, Issue. 19 June 2015.

  5. Amaresh Shivappa Khasabag, Arun Patro, “40Gb OTN Framer Design”, International Conference on Recent Innovations in Engineering and Technology 28th June 2015.

  6. Shalini B, Arun Patro, “Design and Verification of Single UART with Multiple SPI Slave Interface”, International Conference on Recent Innovations in Engineering and Technology 28th June 2015.

  7. Vishwanath Mathapati C, Arun Patro, “Implementation of Multi-channel Broadcast Based UART Controller using Crossbar Switch Technique”, International Conference on Recent Innovations in Engineering and Technology 28th June 2015.


Faculty

Mr. Pradeep S V

Email : pradeep.sv@utltraining.com


The objective of the research group is to explore and design high performance, high speed, low power and highly reliable analog mixed signal circuits to be part of solutions for industrial problems. The research at the group is focused on Transceiver design and developing building blocks such as data converters, PLL’s, DC-DC converters and LDO’s.


Faculty : Dr. Siva S Yellampalli


Students Alumni

S.No Student Name Thesis Title Year of Passing Current Position
1 V S Jagannatha Rao Implementation of Formal Verification on Scalable Arbiter 2014 Faculty as SJBIT
2 Sunita Arvind Rathod Design and Implementation of the Continuous Time Sigma Delta Modulator 2014 Faculty
3 Jamuna G Design and Implementation of Efficient Transconductance Amplifier for Sigma-Delta ADC 2014 -
4 Ranjith N PLC based Automation system for Active stator winding thermal monitoring and protection of ac Motor using handheld WI-FI devices 2014 Faculty at CIT, Gubbi
5 Bhavya H R LMS and RLS Based interference Cancellation in Uniform Linear Array System 2014 -
S.No Student Name Thesis Title Year of Passing Current Position
1 S Janaki Design and Implementation of 7Impulse istributed Waveform Generator 2013 Faculty at AITRIA
2 Nagaraj P Design and Implementation of Sigma-Delta Analog to Digital Converter 2013 Associate Consultant at UTL Technologies Ltd
3 Muralidhara R VIP Architecture and Design Using OVM For IRDA Protocol 2013 Mediatek
4 Tamkanath Sabeeha Design of a Single Board Super Speed USB for Digitizer for Laptop Spectrometry 2013 -
5 Kushal M.L Design and Implementation of PLL for polar Transmitter 2013 -
6 Abdul Qadir. T.K Implementation of Formal Verification on Scalable Arbiter 2013 -
S.No Student Name Thesis Title Year of Passing Current Position
1 Shivasharanappa 1.8 GHz Quadrature PLL Design for Zero-IF GSM Receiver 2012 Faculty BNMIT
2 Sundeep B A Design of STM-1 Framer and Deframer by Interfacing E-3 Frame 2012 Associate Consultant at UTL Technologies Ltd
3 Anand T STM-1 Framer and De-Framer 2012 Applied Material
4 Konda Vijayasree Design and Implementation of E1 to STM-1 Framer and Deframer 2012 -
5 Padmavathi N Priority Encoder Based Adaptable Buffer for Network-on-Chip on FPGA 2012 Faculty
6 Chinmayi Design of On Chip Buck Converter 2012 Faculty at East West College
7 S B Rashmi Design and Implementation of High Frequency PLL 2012 Faculty at Don Bosco College
8 Sathyanarayana R Implementation of Integrated Analog/Digital Random Noise Source (IRNS) 2012 -
9 Ramshanker N ASIC Design in CMOS Technology for Interface of Analog Outputs from Integrated Gas Sensors 2012 -
10 G C Veeresh Design of Low power Area efficient 9Ghz Phase Locked Loop with Four Multi Clock Output In 45nm CMOS Process Technology 2012 -
11 Basavalinga Swamy Linear Assisted DC-DC converter Based on 180nm CMOS Technology 2012 -
12 Lava. R. K DESIGN and Implementation of Low Dropout Linear Voltage Regulator in 28nm Technology 2012 LSI
13 Chethan.S Design & Implementation of 8*16 Latch based register array with reduced Area and power 2012 Qualcomm
14 Mohamed Mohideen Hassaly. A Design rule verification for high Voltage nodes in nanometer technologies 2012 Intel
S.No Student Name Thesis Title Year of Passing Current Position
1 C Kanagasabapathi Modeling and Design of Monolithic Inductor and its application 2011 Westin Power
2 Arun Kumar R Implementation of K-Means Clustering Algorithm for Image Segmentation 2011 Faculty SKIT College
3 Prabavathi P Design of K-Delta 1-Sigma Modulator Based Analog to Digital Converter 2011 Faculty BNMIT college
4 Chethan M Design and Implementation of Sigma Delta Modulator ADC with OSR=64 for Accelerometer Application 2011 -
5 Sophiya Susan Design of a High Speed PLL Using LC VCO in 0.18 um CMOS Technology 2010 Faculty CMRIT College
6 Suma T Hegde Design and Implementation of ALU using Redundant Binary Signed Digit 2010 -
7 Ravichandru B S Implementation of Ethernet Controller with Integrated Security Engines to Enable Fast and Secure Embedded Connectivity 2010 Wipro
8 Prathibha E Design and Implementation of Color Conversion RGB to YCbCr and Vice Versa 2010 -
9 Ravindra S Wireless Based Student Security and Database System 2010 Faculty Atria
S.No Student Name Thesis Title Year of Passing Current Position
1 Gururaj K M Design and Implementation of Warless Transceiver for MEMS Based Pressure Sensor 2008 -
2 Avinash B R Design and Layout of Low Dropout Voltage Regulator 2008 -
3 Chandra Sekhar Sakala Design and Development of 45nm High Speed Standard Cell Library 2008 -
4 Ramakrishna Murthy K A Search for an Optimum Architecture to Implement Sense Amplifier Using IN SRMA 2008 -
5 Damodara ,M S Design of Band gap Reference With Curvature Compensation 2007 Faculty CMRIT College
6 Shyamala Design and Simulation of 6-Bit Programmable GAIN Amplifier 2007 -
7 Mohan Kumar Naik B Design of 6-BIT Two Step Flash ADC 2007 -
S.No Student Name Thesis Title Year of Passing Current Position
1 Yatheesh. H G Design & Simulation of 8-bit 10MHz Successive Approximation ADC 2006 -
2 Ambika Devi R Design & Simulation of Liner Voltage Regulator 2006 -
3 Rajeshwari D. S Design and Simulation of PFD. Charge Pump and Loop filter for 100MHz PLL-Frequency Synthesizer 2006 -
4 Sudharshan K M Design & Simulation of 6-bit 190Mhz Successive Approximation ADC 2006 -
5 Prakash . D Design, Simulation and Layout of Linear Voltage Regulator 2006 Faculty CMRIT College
6 Poornima B RF Frequency Synthesizer Using PLL 2006 -
7 Manjunatha D. V Design of 2.4 GHz CMOS PLL Based Frequency Synthesizer 2006 -
8 Prasanna S Design, Simulation and Layout for CMOS Reference System 2006 -

Agreement with TSMC and UMC for Fabrication Libraries Cadence Research Package


Analog and Digital FE and BE: Advanced Tool Set

Advanced tools Codes
Virtuoso(R) Schematic Editor XL 95115
Virtuoso Multi-mode Simulation with Spectre XPS 90004
Virtuoso(R) Analog Design Environment GXL 95220
Virtuoso(R) Layout Suite GXL 95321
AMS Designer with Flexible Analog Simulation 70020
Virtuoso AMS Designer Verification Option 70030
Incisive Enterprise Simulator - XL 29651
Encounter RTL compiler - XL RC200
Encounter Conformal Low Power - GXL CFM550
Encounter Digital Implementation System XL EDS200
Cadence® Physical Verification System Design Rule Checker XL 96210
Cadence® Physical Verification System Layout vs. Schematic Checker XL 96220
Cadence Quantus QRC Extraction - XL QRCX300
Virtuoso Implementation Aware Design Option 95510
Circuit Simulation
Virtuoso® RelXpert 33580
Virtuoso Accelerated Parallel Simulator 91050
Virtuoso Multi-mode Simulation Power option 91400
Virtuoso Multi-mode Simulation CPU Accelerator option 91500
Virtuoso(R) Power System XL VPS200
Spectre Extensive Partitioned Simulator 91600
Spectre Characterization Simulator Option 3500
Extraction
Cadence Quantus QRC Advanced Analysis GXL option QRCX310
Cadence Quantus QRCX Display Technology Option QRCX330
Cadence Quantus QRC Advanced Modeling20 GXL Option QRCX520
Device modelling
Virtuoso Advanced Device Modeling HVMOS (For Eldo) P6191
Virtuoso Advanced Device Modeling HVMOS (For HSPICE) PASPCG
Graphical Technology Editor PASGTE
Design for Manufacturing
Litho Physical Analyzer LPA108
Litho Electrical Analyzer LEA108
Signoff Power Analysis
Voltus IC Power Integrity Solution Advanced Analysis GXL VTS201
Characterization
Virtuoso Liberate Server ALT110
Virtuoso Liberate Client ALT111
Virtuoso Variety Server ALT210
Virtuoso Variety Client ALT211
Virtuoso Liberate MX Server ALT410
Virtuoso Liberate MX Client ALT411
Virtuoso Liberate LV Server ALT610
Virtuoso Liberate LV Client ALT611
Signal Integrity Analysis
Allegro® Sigrity SI base PA5700
Allegro Sigrity Power Aware SI option SIGR915
Allegro Sigrity system Serial Link Option SIGR935
Allegro Sigrity Package Assessment and Extraction Option SIGR945
IC Packaging
Cadence SiP Digital Architect - XL SIP110
Cadence® SiP Layout - XL SIP225
Cadence 3D Design Viewer PA6605

  1. Design and implementation of an ultra-low power RF energy transceiver for multiple node sensor application.

  2. Design of Bandgap Reference.

  3. Design for a LNA

  4. Phase locked loop analog


  1. United Telecom Ltd
  2. TSMC
  3. UMC
  4. Imspired

  • Two patents filed

  • Industrial Consultancy to Arigamy Semiconductors


  1. More than 100 journals were published in international conference including IEEE and Springer journals.

  2. Nagaraj P, Dr. Siva Yellampalli, “8 Bit Second-Order Continuous-Time Band- Pass Sigma-Delta ADC”, International Journal of Innovative Technology and Exploring Engineering (IITEE) ISSN: 2278-3075, Volume-3, Issue-1, June- 2013

  3. S. Janaki, Dr. Siva Yellampalli, “Design and Implementation of Impulse Distributed Waveform Generator Time Interleaved Impulse Generator”, International Journal of Innovative and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-3, Issue-1, JUNE 2013.

  4. S. Janaki, Dr. Siva Yellampalli, “Design of Impulse Distributed Waveform Generator” 4th IEEE International Conference on Computing Communication and Networking Technologies (ICCCNT 2013) held during 4th to 6th July, 2013.

  5. T. K. Abdul Quidir, Dr. V. Venkateswarlu, “Design and Implementation of Envelope Amplifier and Power Amplifier for Envelop Tracking in polar Transmitters” International Journal of Engineering and Advanced Technology (IJEAT), ISSN: 2249-8958, Volume- 3, Issue- 1.

  6. Jamuna G, Siva S Yellampalli, “Design and Analysis of CMOS Telescope OTA for 180nn Technology,” International Journal of Engineering Sciences Paradigms and Researches (IJESPR) ISSN 2319- 6564 Vol. 15, Issue. 01 July 2014.

  7. Sunita Arvind Rathod, Siva Yellampalli, “Design of Fifth Order Elliptic Filter With signal-Opamp Resonator”, 2014 International Conference on Advanced in Electronics, Computers and Communications (ICAECC), on 10-11 October 2014.

  8. Jamuna G, Dr. Siva S Yellampalli, “Design and Implementation of Telescopic OTA in 8 Bit Second-Order Continuous- Time Band-Pass Sigma-Delta ADC”,International Conference on Electronics, Communication and Computational Engineering– ICECCE, 17 – 18 November 2014.

  9. Spandana Hiremath, “Design of a Fast Settling Low-Voltage Low Dropout Regulator”, International Conference on Recent Innovations in Engineering and Technology 28th June 2015.

  10. S. V. Pradeep , Favoureen Swer, Dr. Siva S Yellampalli, Dr. P. Venkataratnam, “ Design of Low Power, Low Dead Zone High Frequency PFD for a PLL”, International Conference on Communication and Computing July 9-11 2015.

  11. Favoureen Swer, Pradeep S V, Dr. Siva S Yellampalli, “Analog BIST Capacitive MEMS Sensor using PLL”, International Symposium on Women in Computing and Informatics (WCI-2015) 10-13 August 2015.

  12. Prakruthi T G, Dr. Siva S Yellampalli, “Design and Implementation of Sam [le and Hold Circuit in 180nm CMOS Technology”, International Conference on Advanced in Computing, Communication & Informatics 10-13 August 2015.



Faculty :

Dr. Siva S Yellampalli

Email : siva.yellampalli@utltraining.com


Carry out advanced research and development in Embedded System, IoT and Automotive Domain to make life simple


Faculty : Dr. P. Venkataratnam.


Current Students : Manjunath | Ishwar.


Students Alumni : Netravati S H | Vasudev | Anusha | Shruthi.


The Lab is facilitated with Research in Embedded where the following tools are used:

  • Cortex M0/M3 boards
  • 8051 development boards
  • Linux OS
  • Keil
  • Spartan 6 and Spartan 3 FPGA kits

  1. An Efficient Implementation of Fully Functional DDR SDRAM Memory Controller for FPGA’s

  2. Implementation of safety and security for motor bikes using MCU and CAN protocol

  3. RING WITH NFC CAPABILITY

  4. Design space exploration of FAGA-Based NOC Routters

  5. External Memory interfacing with FPGA

Embedded Researh Group of center has direct colabaration with parent company United Telecoms Limited, which is one of India's leading business houses in Telecom Sector, Information Technology and Training Services. Members of ERG will be part of reasearch and developement activities of United Telecoms Limited and have a good reasearch experience related to wearable devices, microcontroller applications and Linux.

1. Leena Chandrashekar, Leelavathi G, “Multi Sensor Data for Robot Application”, International Conference on Recent Advances in Computer Sciences- ICRAS2K12, March 30th -31st 2012.


2. Nagesh Kumar D.N, Mr. Ramesh T, “Remote monitoring and control System for Environmental Parameters in Greenhouse”, National Conference on Recent advances in Electronics & Communication, New Horizon College of Engineering on 18th May 2012.


3. Mahendra M N, Prof. Sudheendra. J and Mr. Shreyem, “Intelligent window based on Embedded”, National conference on Recent Advances in Electronic & communication. Presented at New Horizon College of engineering on 18th May 2012.


4. N. Mohansundaram, Mr. Sudheendra, and Mr. H. R. Shashidhara, “Vision based Automatic Parking System”, National Conference on Recent Advances in Electronics & Communication Engineering on May 2012.


5. Shilpa. M .B, Channabasappa Baligar, “Implementation of Multichannel Temperature Acquisition and Monitoring System based on ARM 7 and CAN bus”, International Conference on Current Trends in Engineering & Management ICCTEM-2012 on July 12th -14th, 2012.


6. RoopaShree S. S, Mr. Manjunath Lakkanavar, “The controlling of Mobile Robot based on ARM9”, International journal of Innovative Technology and Exploring Engineering, on 10 Aug, 2012.


7. Mrs. Vyjayanthi A S, Mr. Channabasappa Baligar, “Wireless battery Charger (RF/Microwave to DC conversion)”, International conference on Advanced computer Engineering and applications on 28th October 2012.


8. Hemanth Kumar G, Mr. Manjunath Lakkannavar “The Design of Granary Environmental Monitoring and control system based on ARM9 and ZigBee”, National Conference ISSN2278-3075 Volume-X Issue-X.


9. Manjunatha R Bhat, Prof Sudheendra j, and Mohammed Tanvee, “Geo Fencing using GPS and GSM /GPRS Wireless Communication System”, International Conference

on electronics and communication engineering.


10. Srikanth Leelavathi. G “Video Monitoring System based on ARM9”, International Journal of Innovative technology and Exploring Engineering vol-X, Issue-X.

11. Manjunath Managuli, Dr. V. Venkateswarlu. “Building Automation with Zigbee using Antilock Security System”, National Conference on “Emerging Trends in Electronics, Communication and Computational Intelligence-ETEC 2013.


12. Abhay A D, Ganesh Krishna, Channabasappa Baligar. “Smart Card Reader Meeting ISO 7816-3 and EMV Level 1 Specifications Using PIC24F Microcontroller”, International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-2278-3075, Volume-X, Issue-X.


13. Anupa. K, Channabasappa Baligar, “Real Time communication between Aero Gas Turbine Engine Controller and Pilot Online Monitoring System”, International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249-8958, Volume- 2, Issue-5, June-2013.


14. Mahesh Bilagi, Manjunath Lakkannavar, “Microcontroller Based Direct Digital synthesizer and FSK Modulator”, International Journal of Engineering and Advanced Technology (IJEAT), ISSN: 2249-8958, Volume-3, Issue-1, October 2013.


15. Harish P, Dr. V. Venkateswarlu, “Design and Motion Planning of Indoor Pipeline Inspection Robot” International Journal of Innovative Technology and Exploring Engineering (IJITEE), ISSN: 2278-3075, Volume-3, Issue-7, December 2013.

16. Neela A G, Channabasappa Baligar, “Fault Tolerant Operation in Aero Engine Using Distributed Computation System” International Journal of Technological Exploration and Learning (IJTEL), ISSN: 2319-2135, Vol-3, Issue-2, April 2014.


17. Risma Rajan, V. Venkateswarlu, “Implementation of Linux based UART Device Driver”, International Journal of Research in Engineering and Technology, ISSN: 2319-1163, Vol. 03, Issue. 07 July 2014.


18. Vidya Priyadarshini. P, Leelavathi. G, Dr. Siva S Yellampalli, “Subcut Aneous Vein Detection using Embedded Linux ARM”, International Journal of Advanced Technology in Engineering and science Vol. 11, Issue. 11 November 2014.

19. Satya Shankaraiah G, Dr. Siva Yellampalli, “Android Based Fluid Dispensing and Blending System Automation”, International Conference on Computational Intellgence and Compuuting Research Held During December 2014.


20. M.S. Mukundaswamy, Ganesh L. Bhat, “Embedded Controller Based Wireless Power Monitoring and Controlling”, International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT-2015),** Paper has been selected for oral presentation to be held during 17th – 18th December – 2015


Faculty

Dr. P. Venkataratnam

Email : venkataratnam@utltraining.com


Image Processing algorithms are repetitive nature.The Image data is very large, so the achievement of high speed of image processing is a difficult task. Field Programmable Gate Array (FPGA) can overcome it. FPGA is an effective device to realize real-time parallel processing of vast amounts of image and video data.


Faculty : Mr. KanagaSabapathi
                     Mr. Amaresh S Khasabag


Current Students : Abhilash C N | Prema C L


Students Alumni : Rashmi | Renusharma | Vasant | Jagadish | Swetha.

The Lab is facilitated with Research Lab where the following tools are used:

  • MATLAB Software
  • Xilinx Software
  • Spartan 3e FPGA boards
  • Spartan6 FPGA boards

  1. Camera Interfacing

  2. Memory Interface

  3. Image and Video Processing

  4. Display standards

4semi Technologies Pvt Ltd

  • IEEE Conference


  1. Six International Journals

  2. Six International Conferences

  3. Manjunatha Reddy E, Nagaraj P, Dr. Siva S Yellampalli, “BER Analysis and MAI cancellation of Voice Signal through CDMA communication using FPGA Spartan 3E Processor”, International Conference on Power Circuit and Information Technologies (ICPCIT-2015) 27th – 28 th April 2015.

  4. Shwetha M N, Leelavathi, “FPGA Based Implementation of Scaling Method for Curve Based Cryptography”, International Journal of VLSI and Embedded Systems (IJVES) Vol. 06, June 2015.

  5. Ishwarya R, Ramana Reddy K, “Vehicle theft detection through face recognition using Raspberry Pi”, International Conference on Recent Innovations in Engineering and Technology 28th June 2015.

  6. Vasanthkumar P, K V Ramana Reddy, Dr. Siva S Yellampalli, “Implementation of High Definition Multimedia Interface using FPGA”, International Conference on Communication and Computing July 9-11 2015.

  7. Renu Sharma, Satish Paidi, K V Ramana Reddy, Dr. Siva S Yellampalli, “Design and Implementa on of 12C Master Controller using APB Bridge on FPGA”, International Conference on Communication and Computing July 9-11 2015.

  8. Jagadeesh R J, K V Ramana Reddy, Dr. Siva S Yellampalli, “Pothole Detection using FPGA”, International Conference on Communication and Computing July 9-11 2015.

  9. Rashmi C, K V Ramana Reddy, Satish Paidi, Dr. Siva S Yellampalli, “Implementation of VGA controller to display image using EDK ”, International Conference on Communication and Computing July 9-11 2015.

Faculty

Mr. Kanagasabapathi

Email :kanagasabapathi@utltraining.com

* Note :

Research Grant for Publishing IEEE Papers : From the management of UTL Technologies Rs.3000/- grant is given for each and every paper which is selected for IEEE Conference/Journal.

Prinicipal

(+91) 77602 80268
(080) 234-72171
siva.yellampalli@utltraining.com